Bridging the Valley of Death: ISI’s Computational Systems Division and the DREAMS Evolution

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Two years into the California DREAMS initiative, Matthew French took the stage at the MOSIS 2.0 Workshop in Arlington, VA on Sept 12, 2025, surveying the landscape of semiconductor innovation that had fundamentally transformed since the program’s inception. As Director of USC Information Sciences Institute’s (ISI) Computational Systems and Technology Division, he has witnessed firsthand the evolution from basic foundry connectivity to something far more ambitious: a comprehensive ecosystem that could shepherd innovations from concept to silicon reality.

The Edison Paradox

“Thomas Edison was really one of the first electrical engineers,” French reflected, drawing parallels between the inventor’s famous quote about perspiration and inspiration, and the modern semiconductor development challenge. In no other field, he observed, did the gap between brilliant ideas and tangible results require such an overwhelming amount of perspiration: technical expertise, infrastructure, and increasingly complex integration challenges.

The initial DREAMS vision had focused on connecting fabrication services and getting foundries online. But French’s team recognized a critical gap: having access to foundational foundry elements was merely the starting point. The real challenge lay in the “valley of death” between innovative concepts and market-ready products.

The Complexity Explosion

French’s division had been tracking an alarming trend. Novel semiconductor designs now required integration with increasingly sophisticated infrastructure that went far beyond traditional GPIO interfaces. Modern chips demanded UCIE multi-chip integration, high-speed I/O interfaces (SERDES, PCIe Ethernet), and modern memory (HBM, DDR), each representing expensive IP licenses that could consume hundreds of thousands of dollars from research budgets.

The CAD toolchain has also exploded in complexity, requiring teams to master an ever-expanding array of specialized tools for the end-to-end design flow. Even after successful fabrication and yield testing, teams face the daunting challenge of system integration, host interfacing, and comprehensive test and validation.

Most critically, French observed that these infrastructure demands were pulling innovation teams away from their core competencies, forcing them to become experts in peripheral technologies rather than focusing on their breakthrough ideas.

The Three-Pronged Solution

To address these challenges within MOSIS 2.0, French’s team developed a comprehensive strategy targeting three critical areas:

1. Rapid Design Prototyping Through Platform Generators

Drawing from their extensive DARPA research portfolio, particularly the PROWESS program, French’s team developed sophisticated rapid design generation capabilities. Their flagship demonstration was the TRACER chip—a Tasklet Reconfigurable Agile Spectrum processor that achieved remarkable performance metrics through systematic reuse of validated components.

The platform System on Chip (SoC) generator, originally developed by Columbia University and enhanced by ISI, provided unprecedented flexibility. Teams could configure architectures with scalable plane configurations, variable bit widths ,and different accelerator cores with seamless targeting of both FPGA and ASIC implementations.The ISI team developed a standardized API and hardware wrapper system that allowed researchers to drop in their novel cores while leveraging validated infrastructure. An SoC could be generated in an hour, supporting design space exploration of multiple architectures in parallel, and shaving weeks to months off a typical design cycle.

2. IP Repository Integration

Recognizing that innovation required more than just connectivity infrastructure, French’s team established a comprehensive IP repository within MOSIS 2. Initial offerings included CPU options such as the silicon-verified ARIAN RISC-V 64-bit and IBEX 32-bit processors, with flexibility to incorporate ARM cores for teams with existing IP agreements. Other accelerator cores include NVIDIA’s deep learning accelerator and the OpenFPGA fabric technologies.

DREAMs is also establishing a DoD IP repository, which includes two novel IP Cores developed by ISI from recent DARPA research:  a high-speed DSP core optimized for wideband RF agile processing, capable of reconfiguring between FFT, FIR, and machine learning operations developed under DARPA PROWESS, and an Fully Homomorphic Encryption accelerator developed under the DARPA DPRIVE program.

The repository strategy extended beyond ISI’s internal capabilities, with active discussions underway to incorporate startup IP and additional validated open-source core.

3. Accelerated Circuit Prototyping

Perhaps the most innovative aspect of French’s approaches the MOSIS 2.0 Accelerated Prototyping Platform (MAPP), which leverages FPGA technology to dramatically reduce the complexity and cost of pre- and post-fabrication testing. Modern FPGAs can emulate approximately 40 million ASIC gates, which is sufficient for most initial prototyping needs and avoids the complexity and dedicated engineering overhead required to support large scale emulation systems.

The architecture cleverly partitioned system complexity: commercial FPGA boards provide low-cost access to validated PCIe, Ethernet, and peripheral IP, while custom daughter cards focused solely on the novel chip under test. This approach dramatically simplified custom PCB design requirements while providing access to sophisticated interface capabilities.

Analog and Mixed-Signal Innovation

Extending their digital success into analog domains, French’s team developed specialized prototyping capabilities using AMD’s RF SOC boards, which integrated FPGA processing with high-speed analog-to-digital and digital-to-analog converters. The CANNPRO project demonstrated standardized controller architectures that could manage analog device configuration, test pattern generation, and signal monitoring across diverse analog prototypes.

The architecture provided unprecedented flexibility: digital processing could be prototyped on FPGA before tape-out, analog functions could be tested through high-speed converters, and the entire system could transition seamlessly from pre-silicon emulation to post-fabrication validation.

The Differentiation Factor

What distinguished French’s team from typical university research labs was their comprehensive infrastructure and security credentials. As a DMEA-accredited trusted IC supplier for both design and aggregation, ISI maintains facilities and personnel capable of supporting the full spectrum of government data protection requirements. The team’s rapid progress toward CMMC accreditation, expected to be fully operational by November 2025, positions them as uniquely capable of supporting sensitive government semiconductor development.

The team’s technical expertise spans the complete semiconductor development stack: computer architecture, front-end and back-end design, fabrication oversight, and specialized CAD tool development for non-standard requirements including ultra-low power, space environment, and security applications. Their contribution to over 20 DARPA programs demonstrated sustained capability to tackle the most challenging semiconductor research problems.

Looking Forward

As French concluded his presentation, the vision became clear: MOSIS 2.0 represented more than foundry access: it embodied a comprehensive development ecosystem designed to compress the time and complexity between innovative concepts and working silicon. Through systematic reuse of validated components, sophisticated prototyping infrastructure, and expert technical support, the initiative promised to restore the focus of semiconductor innovation to what mattered most: the core breakthrough ideas that could reshape entire industries.

The three thrusts, rapid design generation, accelerated prototyping, and expert augmentation, formed a coherent strategy to bridge the valley of death that had claimed too many promising semiconductor innovations. For the first time since the early days of the semiconductor industry, individual research teams could realistically aspire to complete the journey from concept to silicon without becoming lost in the increasingly complex infrastructure requirements that had made such journeys prohibitively difficult.

French’s vision represented nothing less than the democratization of advanced semiconductor development, returning the industry to its innovation-focused roots while providing the sophisticated infrastructure necessary to compete in modern markets.

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Published on December 1st, 2025

Last updated on December 1st, 2025