IC Design
MOSIS 2.0 offers several IC design services. As listed below, our design service capabilities will be able to support customer’s design work in RF/MMIC applications.
Process Design Kit (PDK) Evaluation
We can evaluate the capabilities of PDKs to ensure they support seamless integration into standard EDA (Electronic Design Automation) tool flows. Our evaluation focuses on the PDK’s ability to enable accurate and efficient RF and CMOS logic design, ensuring reliability and compatibility with your design needs.
Our scope of assessment includes the following:
- PDK installation
- IP Implementation integrity
- Circuit and device model accuracy
- DRC and LVS
- MPW closure mock run
Circuit Implementation
We offer comprehensive circuit implementation services, transforming IC schematics into optimized physical layouts ready for fabrication. Our expertise includes modern methodologies like impedance matching and output coupling to enhance performance. Leveraging advanced placement and routing tools, we ensure efficient and reliable circuit implementation tailored to your specific needs.
Circuit Simulation
Our capabilities include running all the mainline circuit simulation tools for comprehensive circuit analysis. We can simulate and evaluate every figure of merit supported by the PDK, such as linearity and nonlinearity, S-parameters, noise figure, VSWR, PAE, gain, output power etc.
Modeling and Simulation
We can estimate electrical effects caused by electromagnetic interference, frequency variations, and other environmental and process-related factors using electromagnetic and process-centric simulators.
Physical Verification
Our comprehensive physical verification service includes a Design Rule Check (DRC), Layout Versus Schematic (LVS) physical verification, and a detailed analysis report for the design. We can perform a DRC for the entire circuit as well as any component to ensure accurate electrical functionality and manufacturability. Additionally, we offer solutions for resolving DRC/LVS violations, either by implementing fixes directly or providing guidance on corrective actions. Our process ensures efficient MPW sign-off at the chip level.