IC Design

MOSIS 2.0 provides comprehensive chip design services that simplify and streamline the development process, enabling our customers to bring their innovative ideas from concept to silicon with confidence. Leveraging state-of-the-art Electronic Design Automation (EDA) tools from Siemens, Cadence, and Synopsys, we offer end-to-end design support tailored to meet the specific needs of each project. Our services include a full suite of physical design capabilities such as floor planning, placement and routing, clock tree synthesis, and power optimization. We ensure that each design adheres to stringent performance and manufacturability criteria, optimizing for both functionality and efficiency.

To maintain the highest standards of quality, our team conducts rigorous Design Rule Checking (DRC) and Layout versus Schematic (LVS) verification, along with additional checks to validate the design before tape-out. Our commitment to quality and precision minimizes errors and accelerates the time to market. We also provide support for custom IP integration, design for testability, and packaging considerations, ensuring a holistic approach to chip design.

By combining our advanced design services with our MPW offerings, MOSIS 2.0 enables a seamless transition from design to fabrication. In collaboration with CA DREAMS hub members, other Microelectronics Commons superhubs, and CHES partners, we leverage additional resources and expertise to address the unique challenges of complex semiconductor projects. Our integrated approach empowers customers to achieve reliable and high-quality results, supporting the successful realization of next-generation semiconductor products.